0.25 micron Libraries

We have helped to revolutionize the foundry industry by offering comprehensive free-of-charge libraries from multiple vendors. In addition, HJTC also offers other libraries available on a fee basis.

Virtual Silicon 0.25um Library
Standard Cell

• 500+ high performance standard cells
• 11-track cell architecture, performance optimized for 150~400 MHz
• Average cell density of 45K gates/sq.mm
• Multiple drive strengths
• Hand-crafted layout
• Scan version of every flip-flop available
• Fully contacted well ties
• Accurate modeling and characterization for timing and power

Two Port Register File

• Synchronous reads/writes
• Static design with zero standby current

Inline I/O

• 70+ 3.3V I/O pads
• Pad pitch: 60um
• Multiple current drives up to 24mA
• Input buffer types - Pull-up/pull-down resistor, pad keeper, clock driver and normal/Schmitt
• Output and bi-directional buffer types with slew rate control
• Silicon proven ESD and latch-up structures
• Automated EDA views
• Routable over the core with higher metal layer

VeriSilicon 0.25um Library (HJTC 0.25um Logic 1P5M Salicide 2.5V/3.3V Process)
High-Density Standard Cell

• Wide Variety of Cell Functions and Drive Strengths.
• Process-Specific Optimization for High-Density, High-Speed, and Low-Power.
• Engineered for Synthesizability and Routability.
• Scan Flip-flops for Design for Testability Support.

I/O Cell

• 3.3V I/O, 2.5V Core, 5V Tolerant.
• Both Inline and Stagger Compatible IO Pads.
• Configurable Input-Output and Skew Rate Control.
• Robust ESD (>2000V) and Latch-up Immunity (±200 mA).
• Competitive Pad Pitch and Height.

Single-Port / Dual-Port SRAM Compiler

• Ultra-High Density, High-speed, and Low-Power.
• Input frequency range: 20 MHz - 200 MHz
• Fully Static Operation and Automatic Power Down.
• PLL module entirely located in the I/O pad rings
• Adaptive Self-time Delay for Fast Access Time.
• Full Suite of Design Views and Models.

Diffusion ROM Compiler

• Ultra-High Density, High-speed, and Low-Power.
• Fully Static Operation and Automatic Power Down.
• Automatic Code Implementation.
• High Capacity Configuration.
• Full Suite of Design Views and Models.

Two-Port Register File Compiler

• Ultra-High Density, High-speed, and Low-Power.
• Fully Static Operation and Automatic Power Down.
• Adaptive Self-time Delay for Fast Access Time.
• Full Suite of Design Views and Models.

Supported Design Tools

Faraday 0.25um Library
Standard Cell

• 400+ high performance standard cells
• 8-track cell architecture
• Average cell density >60K gates/sq.mm
• Optimized multiple drive strengths
• High porosity and routability
• Scan version of every flip-flop available
• Ultra low power cell available
• Gated input for preventing leakage
• Fully tool models support

Inline and Staggered I/O

• 2.5V, 3.3V I/O pads
• 2.5V/3.3VT, 3.3V/5VT I/O pads
• Support over 500+ IO Functions
• Pad pitch: 65um (In-line), 40um (Stagger)
• Programmable current drives and slew rate control from 2mA to 16mA
• Programmable pull-up/pull-down resistor, normal/ Schmitt trigger
• Provide 90+ programming features in one I/O pad
• In-line to staggered I/O corner available

Single Port SRAM, Two Port SRAM, Diffusion and Via2 ROM Compilers

• Synchronous reads/writes
• Static design with zero standby current
• Byte write capability
• Provides both high speed and low power SRAMs
• Ability to compile to multiple aspect ratio
• Scan and BIST support
• Power port connections support
• Zero hold time for inputs