A complete set of DRC/LVS/LPE command files that support major EDA Tools is available for HJTC customers. Files can be retrieved from our website through the My HJTC portal with a pre-arranged account and password. HJTC also provides DRC sign-off support to verify customers' new databases.

Summary of Available Command

DRC/LVS/LPE Frequently Asked Questions (FAQs)

General Questions

1. Why is GDSII the preferred tape-out database format in HJTC?
2. Does HJTC have a preferred layer mapping table (layer name vs. layer number) for customers to follow in their GDSII database? If so, how does it look like?
3. Which command files (DRC/LVS/LPE) and their corresponding EDA tools are supported by HJTC?
4. What can customer do if customer can not find the command file on HJTC Web site that customer wants?
5. What should be done before a customer uses any of the HJTC's command files?
6. What is HJTC's recommended grid size for customer layout and verification?
7. Are there any LVS to LPE flows that HJTC recommend?
8. How long does a customer need to wait for a new created LVS or LPE file from HJTC?

1. What is the DRC sign-off flow in HJTC?
2. How does HJTC guarantee to use a correct database for DRC sign-off? Why is file size a must-be item in DRC sign-off?
3. Are there any "metal coverage rule" requirements for a customer tape-out in HJTC?
4. Why is the "antenna rule check" not included in the generic DRC command file for Dracula at HJTC? What happens if a customer needs the antenna rule check?
5. Does HJTC provide any efficient checking methodology of DRC for logic design with embedded memory?
6. Can OPC block layers be used as memory marker layers?
7. How does HJTC maintain, update and validate its DRC command files?
8. What is the position of HJTC on supporting Assura, Vampire and Diva from Cadence?
9. How to define the term: "metal line end" in TLR?
10. How to define the area of fuse, pad, esd, dummy and slot?

1. Where can the process parameters for RC extraction tools be found?
2. What kinds of command/rule files (vs. vendors) are commonly provided by HJTC?
3. How to modify the command file to get MOS parameters, including AD, AS, PD, PS, by using DRACULA LPE tool?
4. How are the areas and perimeters of the source and drain being calculated? Is 6. Dracula's junction capacitance extraction methodology consistent with ACM=3 defined in HJTC's HSPICE model?
5. How does a customer add the capacitance of the gate-oxide by using DRACULA LPE?
6. How does HJTC simulate conformal dielectric structure with HyperExtract LPE?
7. What is WEE?
8. Does HJTC support WEE on LPE files?
9. What is the difference between Cell level extraction and Transistor level extraction?
10. How does RC extraction tool treat the parasitic L?
11. What is the LPE QA flow in HJTC?
12. What kind of action will be taken in HJTC if there are noticeable differences between silicon data and RC extraction result?

1. What should a customer do if a resistor in the layout is not recognized by HJTC's LVS command file?
2. What actions are needed if a customer wants to compile a net_list with parameters on the sub_circuit line by DRACULA?
3. Why are some devices not recognized by LVS command file downloaded from the HJTC website?
4. Are special components for mixed-mode and RF such as inductors and triple-well MOS recognized by HJTC's LVS command files?
5. What is the LVS QA flow in HJTC?

1. Why is GDSII the preferred tape-out database format in HJTC?

The customer's database must go through DRC sign-off procedure before taping out for pilot run or production. We reviewed this procedure and found that the cycle time was very inconsistent due to the various formats of the database. To shorten the cycle time and improve the productivity and the efficiency, we would like to ask customers for their cooperation in unifying the format of their tape out database.

Currently, three different formats are used for tape-outs. They are GDSII, MEBES, and CFLT. Thus, we do not support tapeouts in CIF or other formats. Please see Table 1 below for the differences in their characteristics.

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2. Does HJTC have a preferred layer-mapping table (layer name vs. layer number) for customers to follow in their GDSII database? If so, how does it look like?

HJTC provides an official layer-mapping table for customers to facilitate GDSII data transferring.

HJTC provides an official layer-mapping table for customers to facilitate GDSII data transferring. HJTC strongly recommends customer to use the official layer mapping in a GDSII database taped out to HJTC. It will save DRC sign off time and make the result correctly.

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3. Which command files (DRC/LVS/LPE) and their corresponding EDA tools are supported by HJTC?

HJTC's Customer Design Support Department (CDS), provides DRC, LVS and LPE command files for both logic and mixed-mode processes in 0.18um and above technologies. They can be downloaded from HJTC's website ( my.hjtc.com.cn) Please check the web for command file availability.

HJTC also cooperates with all mainstream EDA tool vendors (Cadence, Mentor and Synopsys) in allocating resource and finding out possible solutions for HJTC's customers.

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4. What can a customer do if the customer can not find the command file on HJTC Web site that customer wants?

For those command files that are not listed, the customer can request them through their HJTC Customer Engineer (CE).

The CE will evaluate and then forward the request to the Customer Design Support Department (CDS) . CDS will arrange resource to support it and reply the possible release date for the CE to inform the customer as reference.

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5. What should be done before a customer uses a HJTC command file?

To prevent problems during the DRC/LVS/LPE execution, the customer should verify the following items:

1. Examine the consistency of the command file and the design rule by inspecting the specification name and the version number.
2. Read the header of a command file carefully. Important information (listed below) can be found in the header section. For example:
  a. General information including spec name, version, originator, adaptive version of EDA tools, etc.
  b1. Specific rules which are not implemented in the DRC command file.
  b2. The device table that lists all available device definitions in the LVS command file.
  c. Direction of command file usage. For example, option setting to include or exclude a set of special checks, generating methodology of an input layer (N+implant could be a drawn layer or a derived layer generated by tooling).

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6. What is HJTC 's recommended grid size for customer layout and verification?

Please refer to the definition in related TLR or global rule.
If there is no definition in TLR or global rule :
For 0.18um and above technology, HJTC recommends 0.01um as customer's layout grid. HJTC will use 0.001um as verification grid in order to check customer's database to gain better precision.

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7. Are there any LVS to LPE flows that HJTC recommend?

For the neutral standpoint, HJTC does not recommended any flow for customer. Customers could decide their own flow by consider what tools they have.

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8. How long does a customer need to wait for a new created LVS or LPE file from HJTC?

For a normal LVS & LPE (new created) case is about 2 ~ 3 weeks, if related DSM is available.

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DRC Questions

1. What is the DRC Sign-off flow in HJTC ?

When a DRC violation is found in the sign-off procedure, it will be either passed to the customer through his HJTC CE or reviewed by Fab PEI engineers. The DRC sign-off is an important procedure for foundry service to improve production yield and avoid potential problems caused by possible layout rule violations.

Design Rule Check Sign-Off Flow

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2. How does HJTC guarantee to use a correct database for DRC sign-off? Why is file size a must-be item in DRC sign off?

HJTC uses gds file name, date of file, top cell name and file size to identify the customer database and a file ID is assigned to each database. So file size is a key item to check the correctness of the database in case of any data losses during file transferring.

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3.Are there any "metal coverage rule" requirements for a customer's tape-out in HJTC?

Yes, there is a metal coverage rule check that must be satisfied.

The requirement varies according to process. Metal coverage check is included in HJTC DRC command files. Service of transparency checks of masks and dummy metal placement are provided by the HJTC Mask Tooling Engineer (MTE) and the mask house.

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4. Why is the "antenna rule check" not included in the generic DRC command file for Dracula in HJTC?

HJTC does not include the "antenna rule check" in the DRACULA command file because it cannot recognize the geometry of diodes connecting to the net of antenna concern . HJTC would like to prevent the customer from running into trouble due to Dracula's limitations when building up the connection information. Cadence has issued an internal PCR (No. 482163) to fix this problem. Antenna check is not supported by Diva because Diva is a tool for cell-level/macro-level verification.

What happens if a customer needs the antenna rule check?
Ans. HJTC antenna check is supported by Calibre/Mentor Graphics, Hercules/Synopsys and has implemented into DRC command files respectively. HJTC also provides trial-run service by Calibre.
Note: Antenna rule check on Calibre and Hercules does not have this problem.

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5. Does HJTC provide any efficient checking methodology of DRC for logic design with embedded memory?

Layer-marking is one of the approaches to execute the whole chip DRC on an embedded memory cell in a design. It requires a very careful work on the boundary conditions for mask marking and is commonly used by vendors.

HJTC prefers using memory marker-layers where memory mark layers are well-defined in HJTC embedded memory database. In DRC files, 2 sets of the rule checks are applied to logic portion and cell portion respectively and differentiated by the mark layers. With memory marker layers, the violations at memory area are eliminated so that the violations at other area can be reviewed completely.

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6. Can OPC block layers be used as memory marker layers?

It's not recommended due to boundary violations although their shapes are similar to memory marker layers'. Some memory compilers that are out-of-date can't generate memory marker layers. For those memory cells without memory marker layers, it can reduce the violations and expedite the DRC review by using OPC layers as memory marker layers.

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7. How does HJTC maintain, update and validate its DRC command files?

  1. HJTC keeps the version of DRC command files match the parent documents. The internal DRC QA flow is shown at the next page.
  2. DRC QA patterns are updated right after the TLR is revised and applied to validating DRC command files.
  3. HJTC libraries and SRAM cells are also applied. DRC QA patterns, HJTC libraries and SRAM cells are noted as QA database in the DRC QA flow.
  4. The programming engineers are asked to update DRC command files once a bug is found in DRC sign-off. The QA patterns are also updated for the new corner case.

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8. What is the position of HJTC on supporting Assura, Vampire and Diva from Cadence?

  1. HJTC supports Assura for 0.35um and below technology.
  2. Vampire is not supported.
  3. Diva is not supported.

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9. How to define the term : "metal line end" in TLR?

HJTC uses following interpretation for Metal overlap Via rule:
Acceptant criterion of "Metal enclosure (of Via) in line-end direction by 0.1um"
is defined as -

  1. Metal overlap Via by 0.1um in x-direction (+x and -x) OR
  2. Metal overlap Via by 0.1um in y-direction (+y and -y).

In other words, the direction where Metal extends in both opposite sides of Via is treated as the direction of the line.

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10. How to define the area of fuse, pad, ESD, dummy and slot?

Marker layers are applied to the identification of fuse, pad, esd, dummy and slot. Without marker layers, the specific DRC rules such as fuse DRC rule will not be applied to the target area and will check nothing. For the marker layer names and corresponding gds layer numbers, please refer to TLR, global rule and HJTC official layer mapping file.

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LPE Questions

1. Where can the process parameters for RC extraction tools be found?

Process parameters for RC extraction can be found on HJTC's website. Simply login into the TDS account and go to Design Rule/Document Type Category. Parameters (e.g. ILD, IMD, thickness, dielectrics, min width and min spacing for each layer) can be found at categories: "Electrical Design Rule", "Interconnect Capacitance Model" and "Topological Layout Rule".

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2. What kinds of LPE command/rule files (vs. vendors) are commonly provided by HJTC?

The support lists of LPE tools are shown as the following table. Nautilus is not supported due to lack of vendor's support. Dracula and Star-RC are not recommended due to accuracy concern. However, HJTC still support Dracula and Star-RC.

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3. How to modify the command file to get MOS parameters, including AD, AS, PD, and PS by using Dracula's LPE tool?

Add the following commands under the description and operation blocks of the file will have Dracula take the MOS parameters.

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4. How are the areas and perimeters of the source and drain being calculated? Is Dracula's junction capacitance extraction methodology consistent with ACM=3 defined in HJTC 's HSPICE model?

The above figure shows two transistors in series, and they share the same diffusion for the source and drain. With Dracula, a "NRX-EXTRACT" command can extract resistance values of both source and drain of the MOS. The MOS parameters in the output SPICE net_list will include L, W, AD, PD, AS, PS, NRS, and NRD. The internal calculation function is described in Chapter 11 of the Dracula Reference. Users could also define their own PARSET to extract the area and perimeter of MOS source/drain with their own equations.

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5. How does a customer add the capacitance of the gate-oxide by using DRACULA LPE?

First, find the values of Ca and Cf in the spec document "Electrical Design Rule", then add the following commands with both values on <Carea> and <Cperimeter> respectively under the operation block:

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6. How does HJTC simulate conformal dielectric structure with HyperExtract LPE?

Since HyperExtract supports planar dielectric structure only, HJTC uses planar approach to implement conformal dielectric structure. The errors of planar approach are less than 5%.

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7. What is WEE?

WEE stands for Wire Edge Enlargement. Any effect (from manufacturing behaviors) that causes the real dimension not equal to the drawing is known as WEE. Bias, Dishing, Erosion, trapezoid shape are included.

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8. Does HJTC support WEE on LPE files?

Currently, only few RC extraction tools support WEE effect. Some LPE files on HJTC website include the WEE factor. Please read the header of command file for reference. You can contact HJTC for information in detail.

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9. What is the difference between Cell level extraction and Transistor level extraction?

CCell level extraction will only extract the routing layers exclude the cells, Transistor level extraction will extract parasitic RC down to the device level. If customers put the standard cells in the layout and already know the value of the cells, they could use the Cell level extraction flow.

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10. How does RC extraction tool treat the parasitic L?

Currently only few tools claim they can do the L extraction (called RLC extraction tool), and most of the RC extraction tool vendors set the L extraction as their milestone.

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11. What is the LPE QA flow in HJTC?

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12. What kind of action will be taken in HJTC if there are noticeable differences between silicon data and RC extraction result?

We will try to find out the possible causes of differences: the measurement error, process file typo, RC extraction tool accuracy issues or if the process documents is out of date. Once the cause is determined, we will feedback the data to the corresponding department and solve the problem.

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LVS Questions

1. What should a customer do if a resistor in the layout is not recognized by HJTC 's LVS command file?

Some resistors that are customer made cannot be recognized in our official LVS command files. In these cases,CDS can provide help to create a customized command file by customers' request.

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2. How to compile a net_list with parameters on the sub_circuit line by Dracula?

Simply add command ".PARAM" before the circuit description block in the SPICE/CDL net_list file will have Dracula take the parameters on the sub_circuit.

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3. Why are some devices not recognized by LVS command file downloaded from the HJTC website?

LVS files are provided as working templates. Some modification may be required for additional customized devices or recognition / construction issue.

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4. Are special components for mixed-mode and RF such as inductors and triple-well MOS recognized by HJTC' s LVS command files?

Yes, these devices are supported in LVS files of HJTC Mixed Mode/RFCMOS process if FDK PCELL include them.

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5. What is the LVS QA flow in HJTC ?
  1. LVS test structures
  2. QA check list file.
  3. Single device QA pattern.
  4. Library and FDK circuit.

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