Early silicon verification of your prototype designs is the key to bringing your product to market ahead of the competition. However, running test silicon for today's leading edge technologies can be prohibitively expensive. HJTC addressed these issues by enhancing its Chip Shuttle multi-project test wafer program for 2004. We expanded the number of shuttle runs and technologies available and now run each shuttle on HJTC's hot-lot schedule to greatly reduce cycle time.

  The 2006-2007 Chip Shuttle program offers special shuttles targeted at our mixed-signal and RF/CMOS processes. And we now also offer mature shuttle processes to better meet customer's time-to-market and economical prototyping demands.

  HJTC's Chip Shuttle program will reduce your risk and cost by verifying your advanced designs, prototypes, IPs (digital/analog), cell libraries, and I/O's in HJTC silicon.

  For more information regarding the Chip Shuttle program, please contact your account manager or e-mail: chip_shuttle@hjtc.com.cn