设计解决方案

Chip Shuttle®

Silicon Verification

Early silicon verification of your prototype designs is the key to bringing your product to market ahead of the competition. However, running test silicon for today's leading edge technologies can be prohibitively expensive. HJTC addressed these issues by enhancing its Chip Shuttle multi-project test wafer program. We expanded the number of shuttle runs and technologies available and now run each shuttle on HJTC's hot-lot schedule to greatly reduce cycle time.

HJTC's Chip Shuttle program will reduce your risk and cost by verifying your advanced designs, prototypes, IPs (digital/analog), cell libraries, and I/O's in HJTC silicon.

Shuttle Schedule

1H/2019

2H/2019

8"" inch wafer

Jan

Feb

Mar

Apr

May

Jun

Jul

Aug

Sep

Oct

Nov

Dec

0.11um

Logic HS/LL/SP

A

A

     

A

 

0.11um

Flash/EE2PROM

 

A

 

A

 

A

 

0.11um

Logic/MM/NVM

 

A

     

A

   

A

 

0.18um

pFlash/EE2pROM

A

 

A

 

A

 

A

 

0.18um

G2/MM,Shrink

A

 

A

 

A

   

A

   

0.18um

BCD/HV/CIS

A

 

A

 

A

   

A

   

A

Available



For more information regarding the Chip Shuttle program, please contact your account manager or e-mail: chip_shuttle@hjtc.com.cn
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